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> Don't think Pi 5 can run 'supervisor code' (in old ARM language) in 32-bit mode, so RISC OS surely won't run.

The RISC OS folks are well aware of the issue.

There are discussions about what to do underway.

One idea that I sort of like is a tiny sort of hypervisor in Arm64 code, that runs an Arm32 "VM". Then RISC OS executes in the VM.

It's not fully native, no, but with the speeds involved, it would be usable.

There is a lot of prior art for this approach:

1. RISC OS already faced a 24-bit to 32-bit migration, and one bit of the legacy of that is an emulator for running 24-bit RISC OS apps on 32-bit RISC OS, called Aemulor.

https://en.wikipedia.org/wiki/Aemulor

2. There is of course a whole industry running x86 PC emulators on x86 PCs. The one that started it is called VMware and it did quite well.

But others copied it: e.g. Connectix ported VirtualPC from Classic PowerPC MacOS to Windows. I interviewed the company's founder and chief scientist Jonathan Garber.

https://en.wikipedia.org/wiki/Webcam#Early_development_(earl...

At that time, x86 didn't do hardware virtualisation. So, VMware just used a software emulation for ring 0 code. Garber told me that once he saw how VMware did it, he realised Connectix could do that, too. He then told that it was much easier than running x86 code on PowerPC. With a grin he said that it was not only easier, the performance was excellent: the instruction sets were a _really_ close match. ;-) So the emulator was very nearly achieving 1:1 code density: one instruction for one emulated operation.

3. When Apple moved Classic MacOS from 680x0 to PowerPC, it did it using a tiny "nanokernel" containing a 68K-to-POWER ISA emulator.

https://en.wikipedia.org/wiki/Mac_OS_nanokernel



yes, surely a good approach, and as you say the performance is likely to be fine given the vast increase in raw speed since the old days...




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