few classes above.

Only ISA where I've seen a single instruction span two memory pages despite being page aligned

Two cache lines, sure, on earlier models, but not two VM pages!!

Maximum instruction length is 56 bytes. Early models had 8 byte cache lines, later ones 64 bytes. VM page 512 bytes.

I might be mistaken then, but I recall reading something about most extreme decode on VAX going into ~522 bytes.

What I am more certain of was complaints about possibly ending with maaaany TLB lookups (and pagetable walks) for certain "business" optimized instructions.

Absolutely. Six operands [1], each of which can be in a different memory page AND have an indirection via another memory page AND both the indirection and the final operand could if you're unlucky be misaligned and straddle two memory pages ... ow.

[1] MOVTC (Move Translated Character), MOVTUC (Move Translated Until Character), ADDP6 (Add Packed 6-operand)

I think it was implied to me that every operand of ADDP6 could have been indirected, and all the resulting 3 ranges all could straddle pages.